Business Wire

ProDesign Joins Synopsys in-Sync Program to Enable Unified ASIC Prototyping and Verification; Common ASIC Flow Optimized for Customer Productivity

SAN JOSE, Calif.--(BUSINESS WIRE)--April 4, 2005--ProDesign USA, a leading supplier of high-speed FPGA-based ASIC verification platforms, today announced that it has joined the Synopsys in-Sync(R) ...
Design-Reuse

Aldec Extends Spectrum of Verification Tools for Use in Digital ASIC Designs

Henderson, NV, May. 17, 2016 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for digital system designs, today announces that its verification ...
Design-Reuse

Magma and ChipX Extend Integrated RTL-to-GDSII Design Flow to Next-Generation Structured ASIC Designs

Magma Blast Create SA, Blast Fusion SA and ChipX CX6000 Structured ASIC combine to reduce cost and cycle time of high-performance designs SANTA CLARA, Calif., Nov. 9, 2005 - ChipX, the structured ASIC ...
EDN

Pre-configured DFT structures can simplify ASIC design, verification

Steven Kawamoto, Sr. Marketing Manager, Custom LSI Solutions Unit, Gaku Ogura, Sr. Marketing Manager, Design Solutions Center, Richard Lee, Design Engineer, Design ...
Semiconductor Engineering

The Weather Report: 2018 Study On IC/ASIC Verification Trends

Nobel Laureate Bob Dylan observed, “You don’t need a weatherman to know which way the wind blows.” Similarly, we can get a feeling for where our industry is going by attending to the flow of thought ...
Semiconductor Engineering

C-Based SoC Design Flow And EDA Tools

This paper examines the achievements and future of SoC design methodology and design flow from the viewpoints of an in- house EDA team of an ASIC and system vendor. We initially discuss the problems ...
EDN

Network on Chip Router(ASIC) (SOC design)

Implemented a NoC Router in Verilog HDL. An exhaustive testbench was written and the design was tested against it. (Soc design flow – logic simulation, synthesis, timing analysis, verification). An ...