EDN

Structured ASICs allow improved design flow

The past few years have seen substantial shifts in how logic content is delivered into electronic systems. The most dramatic of these changes is the sharp reduction of traditional ASIC design starts — ...
EDN

Chip architecture allows “testless” design flow

As most ASIC designers are aware, there are two primary test-related issues that cause a high degree of pain and schedule delay in creating ASIC designs — the difficulty in adhering to DFT (Design For ...
Design-Reuse

Faraday Adopts Incentia for ASIC Synthesis & Timing Flow

Runtime speed and capacity of Incentia’s logic, test and low power synthesis & timing software crucial for high-performance, complex design success HSINCHU, Taiwan, and SANTA CLARA, Calif. – June ...
Design-Reuse

Magma and ChipX Team to Deliver Unified RTL-to-GDSII Design Flow for Structured ASIC Platforms

Magma design flow supports ChipX CX5000 and future structured ASIC architectures SANTA CLARA, Calif., September 14, 2004 - Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design ...
Electronic Design

FPGA Prototyping Tool Aligns With ASIC Flow

This FPGA-Synthesis Tool Offers The Prototyping Capabilities Required By RF-Intensive Systems And A Migration Path To ASIC Product Design. Over a third of all high-end ASIC designers now use FPGAs for ...
Electronic Design

RTL-To-GDSII Flow Rolls For Structured ASICs

A collaboration between Magma Design Automation and ChipX has produced a unified RTL-to-GDSII structured ASIC design flow. Based on Magma's Blast Create and Blast ...