EDN

Pre-configured DFT structures can simplify ASIC design, verification

Steven Kawamoto, Sr. Marketing Manager, Custom LSI Solutions Unit, Gaku Ogura, Sr. Marketing Manager, Design Solutions Center, Richard Lee, Design Engineer, Design ...
EDN

Test engineers must join ASIC flow early

Paul Taubman is a senior design engineer for Tality Corp., Cadence Design Systems' services organization. In this article he shows how test engineers should interact with designers in order to ...
Design-Reuse

Faraday Adopts Incentia for ASIC Synthesis & Timing Flow

Runtime speed and capacity of Incentia’s logic, test and low power synthesis & timing software crucial for high-performance, complex design success HSINCHU, Taiwan, and SANTA CLARA, Calif. – June ...
Design-Reuse

EnSilica teams with BaySand to provide ASIC UltraShuttle-65 multi-project wafer customers with configurable IP solutions

EnSilica to provide BaySand’s customers with configurable eSi-RISC processor cores, eSi-Connect processor peripherals, eSi-Crypto encryption and eSi-Comms communications IP solutions as well hardware ...