EDN

Specifications: The hidden bargain for formal verification

With 68% of the ASICs going through respins and 83% of the FPGA designs failing the first time around, verification poses interesting challenges. It’s also not a secret that nearly 60-70% of the cost ...
Semiconductor Engineering

A Formal-Based Approach For Efficient RISC-V Processor Verification

The openness of RISC-V allows customizing and extending the architecture and microarchitecture of a RISC-V based core to meet specific requirements. This appetite for more design freedom is also ...
Electronic Design

Formal-Based Observation Coverage Solution Magnifies Verification Closure Precision

Leveraging formal technologies, OneSpin Solutions developed Quantify software to increase the precision of verification-coverage measurements. As part of the company’s 360 DV-Verify line, Quantify ...
EDN

A closer look at security verification for RISC-V processors

Verifying the security of processors has become an essential step in the design of modern electronic systems. Users want to be sure that their consumer devices can’t be hacked, and that their personal ...